The present invention relates to a parallel bus system, and more particularly to a parallel bus system capable of accommodating the addition of peripheral devices to a xe2x80x9cSystem on Chipxe2x80x9d or other similar system.
A xe2x80x9cSystem on Chipxe2x80x9d is generally as shown in FIG. 1, in which a chip 1 includes a central processing unit 11, a decoder 12, and several peripheral devices 13, 14, and 15. Since the interconnections CS1, CS2, CS3 and the bus 10 are fixed, it is very difficult to add other peripheral devices is needed. If two such Chips are connected for expanding, not only are the interconnections very complicated, but also the software programming is very tedious.
Up to the present, some serial bus systems are capable of expanding peripheral devices, but the related instructions and data transmission are very slow due to the series-connection thereof.
It is therefore an object of the present invention to provide a parallel bus system capable of expanding peripheral devices, such that related peripheral devices can be designed to adapt to it very easily for expanding the system.
It is another object of the present invention to provide a parallel bus system such that the peripheral devices can also control the bus for data transmission when needed.
It is a further object of the present invention to provide a parallel bus system that can include two or more central processing units to control the bus by time-sharing.